Anew high speed and low power four-quadrant CMOS analogmultiplier in currentmode
نویسندگان
چکیده
In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1MHz, a −3dB bandwidth of 41.8MHz and a maximum power consumption of 0.34mW. 2008 Elsevier GmbH. All rights reserved.
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تاریخ انتشار 2009